[f-cpu] Supported Instructions

[nico <nico@seul.org>]

Most instruction are defined as "optional". If a fcpu is release without
such instruction it must give an interrupt handler to handel such
instruction.

Imagine that FMUL r1 r2 r3 are supported. So the instruction trap and
...
- "something" (a register?) point on the faulty instruction.
- The handler try to extract the register number to emulate the
instruction
 - by using some others registers ?
 - We need to save some of them (slow?)
 - How to access indirectly the register set ? (to extract data)

So ?

I propose to define (later, much later) the subgroup of instructions. It
will depend on space used and the impact on performance.

nicO
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