Re: Speeding up slow/missed things... Re: [f-cpu] Supported Instructions

[nico <nicolas.boulay@ifrance.com>]

Yann Guidon a écrit :
> 
> hi,
> 
> Andreas Romeyke wrote:
> >
> Cache locking was an issue some time ago and is often used in real-time
> chips (ie TI DSPs). However, there is still the problem of allowing
> users to use it (protection issue which is not found in DSPs and
> embedded CPUs). But this is certainly a desirable issue, at least for
> the L2 cache (if it's used often, it will be cached in L1 too).
> 

I don't like such loking in any way. Prefetch instruction are those kind
of cache manipulation instruction. PII introduice 3 type of locking
(L1,L2 only, L1 + L2). But PIV use the 3 instruction as the same (L2
only load).

Those kind of manipulation are realy close to the cpu architecture so
compatibility for future cpu will became a nightmare. The calculation of
the good prefectching distance are realy hard : too soon and your data
are trashing by following load, too late and when the needed data are
requested the data aren't ready. In both case, you lose time by
consuming data bandwith. 

Locking cache could slow down things. Imagine how a one way cache could
slow done the data fetch, if a large page are locked.

I prefere preload data, immediately usefull.

nicO

> > Bye Art1
> WHYGEE
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