[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

Re: [f-cpu] Supported Instructions



In my mind, invalid instruction always triggers a trap.

If you want to emulate some instructions (whatever you want) and be able to
access the F-CPU registers to read, you can have a speed up using the
possibility that an invalid instruction traps updates three SRs which will
contain the contents of three registers fields of an opcode (valid or not for
this opcode). So when we execute the handler it can quickly have the contents
it needs to compute without need to get them from CMB. Of course we still need
to update those registers in CMB if necessary. If you want to emulate an
instruction without registers fields, well, just let the emulation ignores
those three register operands.

But okay, it is just a suggestion for the problem of a CMB not totally saved
(when our three registers are not saved yet in the CMB), but, I must admit, I'm
not totally convinced with this suggestion :).

----- Original Message -----
From: Juergen Goeritz <goeritz@oekomm.de>
To: <f-cpu@seul.org>
Sent: Sunday, April 07, 2002 7:02 PM
Subject: Re: [f-cpu] Supported Instructions


My idea is to implement nothing at all for unimplemented
opcodes to be free for future changes. And unimplemented
opcodes should always generate an exception.



*************************************************************
To unsubscribe, send an e-mail to majordomo@seul.org with
unsubscribe f-cpu       in the body. http://f-cpu.seul.org/