Re: [f-cpu] RC5, F-CPU and srotl

[cedric <cedric.bail@free.fr>]

> > What I want to do by the port of the dnetc client is to see where we can
> > have problem with our instruction set on high parellisable algorithm. The
> > conclusion of this discussion is that we will have a "real" simd rotl,
> > but not because of this algorithm, but because we want a "clean" CPU.
> Who is "we" in this case?
;-)

> I tend to agree with you, but in general, we have to consider carefully
> what we include and how we do it. If the cost/benefit ratio of a
> particular feature is too high, we'd better drop it.
I agree with you, but I think that about the particular case on wich we 
discuss it's not a bad add (I agree that will depend a lot about your SHL 
unit).

> > > What's a 64-bit CPU good for, compared to a 32-bit one? It's not
> > > necessarily faster, but it can handle large working sets. Therefore
> > > I'd rather focus on scientific applications, databases and so on.
> >
> > Yes, but we need to start from a point, if you have some idee of which
> > algorithm or part of program to port, say it here, and if some one have
> > time he can start to port them.
> In assembler?
Yes, for example, ffmepg or whatever you thing it will be a good idea to look 
at this code to see where we can have problem with our instruction set.

> > > > The case of dnet is looking different but i can't involve myself
> > > > in this now. The case of the SIMD shift has been proved and there
> > > > does not seem to be any difficulty in implementing it with F-CPU,
> > > > we simply disagree on a "small" implementation detail :-)
> > > Huh? No difficulty?
> > I see your last post, so you find a solution, no ? ;-)
> Yes. But I'm still unsure what it will cost (in terms of delay time and
> die area).
I understand that not an easy task, but you will, I am sure, find a solution 
;-)

A+
  Cedric
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