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Re: [f-cpu] RC5, F-CPU and srotl



hi !

just a few quick notes...

Ben Franchuk wrote:
> Andreas Romeyke wrote:
> > Hello,
> >
> > > - a FORTH interpreter
> > That is a very well idea. forth is easy to learn, forth-programs are easy
> > to debug and a forth-interpreter is easy to write. And forth is a good
> > point to start experiments with development on F-CPU...
> >
> > But, could we really map a stack-based language to a register-machine like
> > F-CPU is?
> Easy answer maybie. The F-cpu has no problems with stacks, the problem
> is that most machines have deep pipelines (like the F-cpu)
i don't think that FC0's pipeline is such a deeply pipelined computer.
In some situations, the pipeline is shorter than a plain Pentium
and it's much simpler than a P2 or P3.

This makes me think that adding register renaming or even register bank
switch/rotation to FC0 will add a pipeline stage or two, break the schedules
and explode the jump latencies. This is one of the reasons why i want to keep the
core as simple as possible, without bells and whistles (such as loadm and storem).
If "indirect" register bank accesses are necessary, the bank access is
performed only at the fetch stage (so the fetched instruction is blocked for a cycle).
</just a note>

> and Forth is
> known for bouncy code flow and data access that really mess up a cache.
it is also known for requiring a small footprint :-) so if your cache is
large enough (and if your L2 can sustain the load), the problems will
come from somewhere else (but we'll have to measure this).


> Ben Franchuk - Dawn * 12/24 bit cpu *
WHYGEE
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