Rep:Re: Rep:Re: [f-cpu] RC5, F-CPU and srotl

["Nicolas Boulay" <nicolas.boulay@ifrance.com>]

I think you should sleep  ! ;p

The 12 cycle of the mul come from the bandwith (one result every 12
cycle) of the unit. This unit aren't pipeline at all !

Currently PIII have 1 cycle bandwith AND 1 clock latency (PIV have 2
clock latency)

nicO

-----Message d'origine-----
De: Yann Guidon <whygee@f-cpu.org>
A: f-cpu@seul.org
Date: 17/04/02
Objet: Re: Rep:Re: [f-cpu] RC5, F-CPU and srotl

hi !

Nicolas Boulay wrote:
> De: Yann Guidon
> > > But, could we really map a stack-based language to a
> > > register-machine like F-CPU is?
> > Easy answer maybie. The F-cpu has no problems with stacks, the
problem
> > is that most machines have deep pipelines (like the F-cpu)
> i don't think that FC0's pipeline is such a deeply pipelined computer.
> In some situations, the pipeline is shorter than a plain Pentium
> and it's much simpler than a P2 or P3.
> >>> Most of EU aren't pipelined in the pentium. But our mul unit need
6
> cycles...

from memory, imul took 12 cycles for 32-bit operands on a P53.
i remember that i measured this in 1996 and i was surprised
that 16-bit mul was slower than 32-bit mul.

Other operations like add and logic are 1 cycle.
So just compare the 2-cycle 64-bit addition of FC0
to the 1-cycle add of the Pentium (and other similar
CPUs) on one hand, and the 6-cycle 32-bit MAC compared to the
12-cycle, 32-bit IMUL of the P53 on the other hand...
(FC0 is 2x "faster" on multiplies and "slower" on more common
operations, if clocked at the same frequency)

and there is a last detail : when mul executes on P5, the
rest of the pipeline stalls. decode is frozen so you can't
make other work in parallel ...

WHYGEE
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