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Re: [f-cpu] F-CPU vs. Itanium
> > argh .. fucked pine .. I was writting reply 30 minutes and it crashed ;(
> > Now I'm going to write again.
> this doesn't only happen with pine ;-)
> Fortunately, Netscape designed the "save as draft" button ;-P
what's irony ! Pine crashed when I did ^O (save as draft) ;-\
But is it because I compiled new message coloring and threading
version of pine - old one didn't crashed. I'll have to apply gdb ;)
> mmm IIRC, Bochs is not GNU ?
hmm probably not - but it seems to be free enough ;)
> It makes the same problem as a plain C simulator : we already have to deal with
> a VHDL source tree and there are too few contributors yet. we can't hire
> anybody, you know : it's all volunteer work. when work is done.
true .. The biggest problem I see: is there any free tool to use
for simulation cpu (or other logic) in VHDL ? If not it too hard
to write one ?
I ask because when I developed first version of advanced packet scheduler
I did it in userspace - I was able to quickly evaluate speed and has been
forced to rethink/rewrite whole agorithm three times (the complexity
analyse is almost impossible there) - it saved a lot of time - then
I implemented it once in kernel space (which is a bit harder/slower).
I was thinking about emulator where all ideas can be quickly evaluated
million times before you start coding actual logic.
And if there would be single tool used by all participants I think that
some ideas could be tested very fast.
> slow if we can't access full-custom technologies (like Intel and IBM do).
> Beyond, another strategy must be used.
I'm not experianced here, what is difference between ASIC and full
custom ? ASIC can use only predefined blocks ?
> > university did it but they have working 3 ported 32x31 register set
> > operating at 16GHz with only 20W of thermal loss.
> "only" ?...
hmm not too low abs. number ;) But they computed 16GHz in cmos would have
much more .. Also they claim that with higher integration this number
will decrease and in cmos it increases ..
> > Wonderfull ! The only word I can say :->
> you're the only one who looks enthusiastic ;-)
probably because I still know too little about making CPUs ;)
> > But you can do it only if you are sure [r3] is not later changed
> > by store. And you never know (at compile time) that two pointer's
> > might be the same (if they are the same type).
> in FC0, the LSU is a 8*256 buffer where each line can be associated
> to a register (or several). so if there's an alias, there is no problem.
yes yes, I already understood from Riepe's mail.
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