Re: [f-cpu] Winograd DCT on my seul.org account

["Marco Al" <marco@simplex.nl>]

Yann Guidon wrote:

> of course. but usually, we speak about "classic RISC" on this list.

When I think about classic RISC I think about superscalar execution,
since that is what all the classic RISC architectures used to evolve.
And within the community which created those classic RISC design the
consensus that superscalar has hit diminishing returns has been around
long enough that even that very idea can be termed classic :)

Dynamic multithreading uses threads not a whole lot bigger than
mentioned here.

>>> "We can even use threads of about 10 instructions to achieve
efficient
>>> parallel execution"
>>> from http://www.computer.org/micro/mi2000/pdf/m4012.pdf
>
> oh, _that_ paper...
>
>> Nice. If you do it in hardware, you can of course fork and
synchronize
>> threads much faster.
>
> i don't remember well, but even though synchronisation is rather fast
> (through common registers or something like that), _communication_
> and _programming_ is another subject... and i don't even speak about
> extensibility (and binary compatibility) because it looks like
> an ASIC that has a very specific application (speech recognition).

It looks like an embedded processor to me, might be slightly tailored to
a specific task ... but its no more a speech recognition ASIC than say
the SH4 is a 3D T&L ASIC IMO.

>>> Nice. If you do it in hardware, you can of course fork and
synchronize
>>> threads much faster.
>>
>> that's the way in the future anyway...
>
> and it will remain so for a long time ;-P

You might want to tell Intel that.

Marco

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