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Re: [f-cpu] IDU News; synthesis report
On Wed, Apr 09, 2003 at 11:44:13AM +0200, devik wrote:
> > > Ok, ASU on 2E: 104.745MHz
> >
> > Looks good.
>
> yes :) And 117 MHz on Virtex2.
Even better :)
> > > By the way, I synthetized scalar 64 bit adder and 32bit multiplier
> > > for compare.
> > > Adder (not pipelined): 120 MHz, 155 slices
> > > Adder (2 stages): 160 MHz, 198 slices
> >
> > That's a plain adder, right? No subtract, saturate or average
> > functions?
>
> exactly. It is ripple carry adder. I did pipelined one by
> splitting it into 2 32 bit parts.
> XST detects "+" operators and uses internal fast-carry
> chain. It needs only 50 ps (picoseconds) per carry.
Can you try a simple carry-select adder? I'll attach a copy.
> Pipelined one runs at 164 MHz and 113 slices in Virtex2.
>
> > > Mult (not pipelined): 50 MHz, 344 slices
> >
> > What kind of multiplier?
>
> Don't know. I simply used "*" and XST synthetized one using
> its dedicated resources (fast carry and "AND-chain").
> I also tested it with Virtex2. It used 3 on-chip 18x18
> multipliers and goes 90MHz (single cycle 32 bit MUL).
But unfortunately it doesn't do what we want either.
--
Michael "Tired" Riepe <Michael.Riepe@stud.uni-hannover.de>
"All I wanna do is have a little fun before I die"
-- simple_adder.vhdl -- 64-bit carry select adder
-- Copyright (C) 2003 Michael Riepe <michael@stud.uni-hannover.de>
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- @(#) $Id$
library IEEE;
use IEEE.std_logic_1164.all;
entity Simple_Adder is
generic (
WIDTH : natural := 64
);
port (
A : in std_ulogic_vector(WIDTH-1 downto 0);
B : in std_ulogic_vector(WIDTH-1 downto 0);
--
Y : out std_ulogic_vector(WIDTH-1 downto 0);
Z : out std_ulogic_vector(WIDTH-1 downto 0)
);
end Simple_Adder;
architecture Behave_1 of Simple_Adder is
-- carry look-ahead circuit
-- d=1-2
procedure CLA (Gi, Pi : in std_ulogic_vector;
Go, Po : out std_ulogic_vector) is
constant L : natural := Gi'length;
begin
--pragma synthesis_off
assert L mod 4 = 0;
assert (Gi'left = L-1) and (Gi'right = 0);
assert (Pi'left = L-1) and (Pi'right = 0);
assert (Go'left = L/4-1) and (Go'right = 0);
assert (Po'left = L/4-1) and (Po'right = 0);
--pragma synthesis_on
for i in L/4-1 downto 0 loop
Go(i) := Gi(4*i+3)
or (Pi(4*i+3) and Gi(4*i+2))
or (Pi(4*i+3) and Pi(4*i+2) and Gi(4*i+1))
or (Pi(4*i+3) and Pi(4*i+2) and Pi(4*i+1) and Gi(4*i+0));
Po(i) := Pi(4*i+3) and Pi(4*i+2) and Pi(4*i+1) and Pi(4*i+0);
end loop;
end CLA;
-- carry select vectors
-- d=2
procedure CSV (G, P : in std_ulogic_vector;
S, T : out std_ulogic_vector) is
constant L : natural := G'length;
begin
--pragma synthesis_off
assert L mod 4 = 0;
assert (G'left = L-1) and (G'right = 0);
assert (P'left = L-1) and (P'right = 0);
assert (S'left = L-1) and (S'right = 0);
assert (T'left = L-1) and (T'right = 0);
--pragma synthesis_on
for i in L/4-1 downto 0 loop
S(4*i+0) := '0';
S(4*i+1) := G(4*i+0);
S(4*i+2) := G(4*i+1)
or (P(4*i+1) and G(4*i+0));
S(4*i+3) := G(4*i+2)
or (P(4*i+2) and G(4*i+1))
or (P(4*i+2) and P(4*i+1) and G(4*i+0));
T(4*i+0) := '1';
T(4*i+1) := G(4*i+0)
or P(4*i+0);
T(4*i+2) := G(4*i+1)
or (P(4*i+1) and G(4*i+0))
or (P(4*i+1) and P(4*i+0));
T(4*i+3) := G(4*i+2)
or (P(4*i+2) and G(4*i+1))
or (P(4*i+2) and P(4*i+1) and G(4*i+0))
or (P(4*i+2) and P(4*i+1) and P(4*i+0));
end loop;
end CSV;
begin
adder : process (A, B)
variable G0, P0 : std_ulogic_vector(WIDTH-1 downto 0);
variable G1, P1 : std_ulogic_vector(WIDTH/4-1 downto 0);
variable G2, P2 : std_ulogic_vector(WIDTH/16-1 downto 0);
variable G3, P3 : std_ulogic_vector(WIDTH/64-1 downto 0);
variable S0, T0 : std_ulogic_vector(WIDTH-1 downto 0);
variable S1, T1 : std_ulogic_vector(WIDTH/4-1 downto 0);
variable S2, T2 : std_ulogic_vector(WIDTH/16-1 downto 0);
variable Y1, Z1 : std_ulogic_vector(WIDTH-1 downto 0);
variable Y2, Z2 : std_ulogic_vector(WIDTH-1 downto 0);
variable Y3, Z3 : std_ulogic_vector(WIDTH-1 downto 0);
begin
-- input stage (half adders)
-- d=1
P0 := A xor B;
G0 := A and B;
-- carry look-ahead tree
-- d=3
CLA(G0, P0, G1, P1);
-- d=5
CLA(G1, P1, G2, P2);
-- d=7
CLA(G2, P2, G3, P3);
-- carry select vectors
-- d=3
CSV(G0, P0, S0, T0);
-- d=5
CSV(G1, P1, S1, T1);
-- d=7
CSV(G2, P2, S2, T2);
-- 4-bit partial results
-- d=4
Y1 := P0 xor S0;
Z1 := P0 xor T0;
-- 16-bit partial results
-- d=6
for i in WIDTH/4-1 downto 0 loop
if to_X01(S1(i)) = '1' then
Y2(4*i+3 downto 4*i) := Z1(4*i+3 downto 4*i);
else
Y2(4*i+3 downto 4*i) := Y1(4*i+3 downto 4*i);
end if;
if to_X01(T1(i)) = '1' then
Z2(4*i+3 downto 4*i) := Z1(4*i+3 downto 4*i);
else
Z2(4*i+3 downto 4*i) := Y1(4*i+3 downto 4*i);
end if;
end loop;
-- 64-bit result
-- d=8
for i in WIDTH/16-1 downto 0 loop
if to_X01(S2(i)) = '1' then
Y3(16*i+15 downto 16*i) := Z2(16*i+15 downto 16*i);
else
Y3(16*i+15 downto 16*i) := Y2(16*i+15 downto 16*i);
end if;
if to_X01(T2(i)) = '1' then
Z3(16*i+15 downto 16*i) := Z2(16*i+15 downto 16*i);
else
Z3(16*i+15 downto 16*i) := Y2(16*i+15 downto 16*i);
end if;
end loop;
Y <= Y3;
Z <= Z3;
end process;
end Behave_1;
-- vi: set ts=4 sw=4 equalprg="fmt -72 -p--": please