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Re: [f-cpu] IDU News; synthesis report



> On Thu, Apr 10, 2003 at 02:46:11PM +0200, devik wrote:
> [...]
> > > Can you try a simple carry-select adder?  I'll attach a copy.
> >
> > Ok, 310 slices, 65 MHz on Spartan2E. Seems ripple one
> > is superior on fpga because they have dedicated circuits
> > for it. Maybe one could create 8 8bit ripple adders
> > and add carries in next stage - these +1 adders could
> > use fast carry chain again ...
>
> Design criteria for FPGAs are very different.  In most FPGAs, every
> logical function with 3 or 4 inputs will have the same delay, for example.
> In some chips, a 1-bit full adder is as fast as a 2-input nand gate,
> .....

Oh yes I know. My comment was not in way "change f-cpu design".
It was only academic thought how could one make fast FPGA specific
SIMD adder.
One other specific of FPGA is that each (or each two) LUT has private
flip-flop. Thus it seems to me that ultra high throughtput units
on FPGA could take it into account and be pipelined deeply (because
these FFs come at no price).
Also is there some web page where could I learn things like types
of adders and multipliers ?

> Earlier synthesis runs with Synopsys reported 389 MHz for IAdd and 458 MHz
> for IMul64 (that were the previous versions; the current ones are probably

these are for ASIC ? As I some time ago discussed with nicO, how
can one have 6 GHz adder like one in P4 ?
Is the trick in hand placing transistors instead of using
vhdl synthetizer ?

devik

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