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Re: [f-cpu] Alternative ROP2 Implementation
On Mon, Apr 21, 2003 at 08:30:14PM +0200, Yann Guidon wrote:
[...]
> i believe that this implementation is actually slower than the precedent
> version.
> The reason is simple : you implement a 16-input MUX equivalent,
> but the precedent version uses a 4-MUX as its core.
On the other hand, I don't need a 3:4 bit decoder for the function
bits (which sits in front of the select inputs in your version).
> >The main advantage of this kind of circuit is that the `b' operand signals
> >may come later than the rest. That allows to put a SIMD <n>:2**<n>
> >decoder in front of it which will help providing the full set of `bitop'
> >instructions:
[...]
> >with a latency of just 1 cycle (which won't work with the SHL unit).
> >
> is it the only reason why you re-built this unit ?
The reason was that I wanted to have the bitop instructions in the
ROP2 unit. And of course I had to try if my idea works ;)
[...]
> i'd really be interested to see the speed differences ....
> and we'll take the faster version, of course :-)
Only if you build a single-stage version that handles combine mode
up to 64 bit chunks and doesn't put the decoder in the XBar stage --
otherwise that would be an unfair competition ;)
> but i don't want to burry the old plain MUX-4 version
> which can still be useful.
Who said that we're going to throw it away?
In fact, it wouldn't be a bad thing at all if we had several versions
of the execution units. I also remember that you said you wanted to
re-implement EU_SHL, using a different approach. Doing that won't make
anything worse -- but maybe better. At least it will give users a choice,
and that's a good thing per se.
> btw, does your bitop version support SIMD operations ?
Of course! It's equivalent to a `full' SIMD shift (with separate shift
counts for every chunk, unless the operand is immediate) followed by an
ordinary logical operation.
--
Michael "Tired" Riepe <Michael.Riepe@stud.uni-hannover.de>
"All I wanna do is have a little fun before I die"
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