[Author Prev][Author Next][Thread Prev][Thread Next][Author Index][Thread Index]

Re: [f-cpu] Interim solution to prototype the core



'+' or '*' or SRAM block it the same.

Beside that some synthetizer are scriptable, so you could guide the synthese.

If you optimise for a current FPGA, the design will be obsolete when ready.

2015-04-10 14:58 GMT+02:00 <whygee@xxxxxxxxx>:
Le 2015-04-10 14:50, Nicolas Boulay a ÃcritÂ:
Try a simple design before a complexe one.
what do you think I've been doing these last 12 years ? ;-)

'+' is much easier to manage than a block instantiation.
oh, i'm not speaking about that.

Synthesizer could be very clever with high level code.
"could".
As long as you teach them well and fine tune progressively.
And make sure that what you ask them matches precisely
what they recognise and that the chip does well,
and you check all the delays before.
But that's not a problem for me.


yg
*************************************************************
To unsubscribe, send an e-mail to majordomo@xxxxxxxx with
unsubscribe f-cpu   Âin the body. http://f-cpu.seul.org/