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Re: [f-cpu] Register Bank



hi !

Michael Riepe wrote:
> To illustrate what I said before, I wrote a little register bank entity.
thanks ! now we have something that we can discuss about :-)

> It's not the real thing (there is no scoreboard interface, it's not
> SIMD capable, and register 0 isn't handled either)
this can be added rather easily.

> but it already has
> 3 read and 2 write ports that can be used simultaneously (except for
> the special case that both writers try to write to the same register;
> in that case, write port 0 has priority).
this case doesn't need to be handled at this location.
the scheduler takes care to delay the operation if a conflict occurs.


this may sound silly, but what about using transparent latches,
and not flip-flop, for the register set ?

>  Michael "Tired" Riepe <Michael.Riepe@stud.uni-hannover.de>
WHYGEE
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