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Re: [f-cpu] Register Bank
Hello everybody,
First of all, a little introduction :
my name is Stéphane Bersin; I am an ASIC designer
and I\'ve been working in telecommunications design center
on GSM and UMTS for 4 years now.
I read some of the posts of the f-cpu list, but I have
too few time to participate to your technical exchanges. 8-(
I read this afternoon a post from Michael Riepe with
the regbank.vhdl file attached and I would like to make a
technical add. I had to change my vhdl code ( in my current project )
two months ago in order to comply with ASIC vendors .
Some vendors (ST micro, IBM, Atmel, ...) seem to dislike
asynchronous resets in designs. They strongly prefer synchronous
resets. Resets are managed in a unique module but we have to modify
sequential processes; the original code is :
-- writers (sequential)
process (Write_0, Write_1, Write_Enable_0, Write_Enable_1, Clk, Rst)
begin
if Rst = \'1\' then
Regs <= (others => (others => \'0\'));
elsif rising_edge(Clk) then
for i in NREGS-1 downto 0 loop
if to_X01(Write_Enable_0(i)) = \'1\' then
Regs(i) <= Write_0;
elsif to_X01(Write_Enable_1(i)) = \'1\' then
Regs(i) <= Write_1;
else
-- register remains unchanged
end if;
end loop;
end if;
end process;
... and becomes :
-- writers (sequential)
process ( Clk )
begin
if rising_edge(Clk) then
if ( Rst = ACTIVE_RESET ) then
Regs <= (others => (others => \'0\'));
else
for i in NREGS-1 downto 0 loop
if to_X01(Write_Enable_0(i)) = \'1\' then
Regs(i) <= Write_0;
elsif to_X01(Write_Enable_1(i)) = \'1\' then
Regs(i) <= Write_1;
else
-- register remains unchanged
end if;
end loop;
end if;
end if;
end process;
FPGA tools seem to work fine with this coding style, but I did not
make further tests.
Note that the use of a constant for the reset value is the best way
because you don\'t always know if the reset is active high or low before the
choice of a vendor.
Do not forget that a majority of vendors do not support tri-states
( \'Z\' ) in the core of a design, so we have to replace them with muxes.
Could somebody tell me why there are
\"Write_0, Write_1, Write_Enable_0, Write_Enable_1\"
signals in the sensitivity list ?
Replies are welcome.Good night.
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