[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

Re: [f-cpu] Register Bank



hi !

i'm happy that the discussions have started again on this list,
and it's even better because they are constructive.

Ben Franchuk wrote:
> Yann Guidon wrote:
> >
> > this may sound silly, but what about using transparent latches,
> > and not flip-flop, for the register set ?
> 
>  Latches map better for ASIC's rather than FPGA's. Registers
> are nice since you only have one clock to worry about. Latches
> tend  need a inverted clock so so may have clock skew problems.
> Ben.
> 
> Standard Disclaimer : 97% speculation 2% bad grammar 1% mostly true facts.
> "Pre-historic Cpu's" http://www.jetnet.ab.ca/users/bfranchuk
> Now with schematics.

It is sure that we will have to prepare several "versions"
("architecture" in VHDL) of the register set. maybe some will
be "tuned" for a particular technology. At this point, latches
vs Flip-flops is pointless, but it could become an option for
special cases...



WHYGEE
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
*************************************************************
To unsubscribe, send an e-mail to majordomo@seul.org with
unsubscribe f-cpu       in the body. http://f-cpu.seul.org/