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Re: [f-cpu] Register Bank



On Thu, 2 Aug 2001, Michael Riepe wrote:

> > this may sound silly, but what about using transparent latches,
> > and not flip-flop, for the register set ?
> 
> I don't know... I don't like latches very much.  They're hard to
> control (and the name reminds me of "glitches" ;).

Latches are also problematic from the testability side. In all design the
testability should be considered. You can't do an ASIC if your testability
sucks. So synchronous logic without latches should be preferred and
asynhronous logic should be avoided. Asynch. logic is even more difficult
with FPGAs.

=============================================================================
Mr. Kim Enkovaara   | kim.enkovaara@iki.fi | Microelectronic Riemannian
Vasamatie 1 C 16    | IRC: embo            | curved-space fault in
02630 Espoo         |                      | write-only file system

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