[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

Re: [f-cpu] snapshot QDCPOC+YGASM



On Thu, 2 Aug 2001, Michael Riepe wrote:
> 
> > my proposition is to reverse the order of all the bits
> > in the manual. the instructions will be stored in big-endian
> > so the opcode always appears at the first position in a hexdump.
> > we had this kind of discussions 2 years ago and i think that the
> > effort is not large. in fact it probably eases the encoding and
> > the decoding.
> 
> In that point, the manual is confusing anyway.  The bits are numbered
> from left to right, implying that the least significant bit/byte is on
> the left (contrary to usual western notational conventions which place
> it on the right).
> 
> I have no problems with making the opcode either the LSByte or the MSByte
> of the instruction, but we should stick with little-endian because
> it's the default for the load and store instructions (without the `e'
> flag set).  That is, if an instruction is stored at address (A), the
> MSByte (which is probably the opcode) is stored at (A+3), and the
> immediately following instruction starts at (A+4).

Hi,

may I rise another topic? What about providing a 'trace modul'
in VHDL to split up the opcodes for debugging and tracing
purposes? In that case only the trace module and the instruction
decoder must match. This is much easier to handle in automatic
test suites. And I hope there is a test strategy to verify
each modules interface to other parts. Can someone point me
to this chapter in the documentation?

JG

*************************************************************
To unsubscribe, send an e-mail to majordomo@seul.org with
unsubscribe f-cpu       in the body. http://f-cpu.seul.org/