Re: [f-cpu] Re: FC0 XBAR

[Juergen Goeritz <goeritz@oekomm.de>]

On Thu, 2 Aug 2001, Michael Riepe wrote:
> > > > > The SPARC architecture describes a register set that provides
> > > > > read and write to the register bank in a single cycle since
> > > > > its a pipelined architecture capable to execute an instruction
> > > > > each cycle.
> > > >
> > > > now the problem is when the written register is the same as the read register.
> > > > gut feeling tells me that the signal couldn't propagate fast enough.
> > > > some kind of bypass could become necessary.
> > > 
> > > Yes, but write usually is at least one cycle delayed, isn't it?
> > it depends, but it doesn't solve the problem : the delay only "moves"
> > the problem from one cycle to another...
> 
> IMHO, reading and writing "in the same cycle" means that *by the end
> of the cycle* (when the clock signal rises) the new data is stored in
> the register, while the reader gets a copy of its *previous* contents
> at the same time.

Actually, if you look at the design of synchronous dual ported
RAMs you will find some kind of port 0 access in first half and
port 1 access in second half of clock. It's a bit more complicated
if you want to have a complete asynchronous behaviour on both ports.

> > we CAN detect when the bank is accessed both for read and write.
> > we can even delay the instruction that does that (but it's not desirable).
> > however, on some cases it might be that the hardware doesn't need
> > such a measure. it depends too much on the silicon characteristics...
> 
> If there is a read-after-write dependency, we have to a) bypass the
> result of the first instruction (if the result arrives in time) or b)
> delay the second instruction (if bypassing is not possible or the result
> ist NOT ready).

Maybe I didn't get it yet!? Aren't you guys designing synchronous
computing units with registered outputs? Handling the transfer
back to the register bank in the next clock? Thus having a
pipeline of decoding->read_from_reg&exec->write_to_register->...?
Could someone point me to my misunderstanding please?

JG

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