Re: [f-cpu] Register Bank

[Juergen Goeritz <goeritz@oekomm.de>]

On Fri, 3 Aug 2001, Ben Franchuk wrote:

> Kim Enkovaara wrote:
> > Latches are also problematic from the testability side. In all design the
> > testability should be considered. You can't do an ASIC if your testability
> > sucks. So synchronous logic without latches should be preferred and
> > asynhronous logic should be avoided. Asynch. logic is even more difficult
> > with FPGAs.
> 
> Considering the fact that Flip Flops contain several latches
> they too are hard to test. I like latches over flip flops
> as data flows thru the system system rather than stop & go with
> D flip flops.While a multi-phase clock is required clock skew
> problems are less in many cases.Latches can be 1/2 the size
> of flip flips.

Remember that there are other types of flipflops as well like
JK-FF and T-FF. Those types can sometimes reduce the combinational
logic required. A good synthesizer can vary the flipflop types
for each single signal.

A latch will use the information on a glitch!

JG

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