Re: [f-cpu] Re: FC0 XBAR

[Michael Riepe <michael@stud.uni-hannover.de>]

On Mon, Aug 06, 2001 at 10:37:05AM +0200, Juergen Goeritz wrote:
[...]
> > If you find a way to encode instructions like
> > 
> > 	r5 = r1 * r3 - r2 * r4
> > 	r6 = r1 * r4 + r2 * r3
> > 
> > directly, without using temporary registers, I will use it! :)
> 
> Hi Yann, that reminds me of something complex...

Yep, a data flow (or reconfigurable) machine :)

[...]
> > The Xbar behaves just like another pipeline stage, and the register
> > bank like a pipeline register.  Now, let's add the bypass:
> > 
> >    reg                 reg
> >     +    +----+----+    +
> >     |----| instr 1 |----|
> >     +    +----+----+\   +
> >      Xbar            \
> >                   reg \               reg
> >                    +   \+----+----+    +
> >                    |----| instr 2 |----|
> >                    +    +----+----+    +
> >                     Xbar           Xbar
> > 
> > The result register is moved out of the data path, we save 1 cycle.
> > We cannot save more because there's a 1-cycle delay each time data
> > passes the Xbar.
> 
> Can you guarantee any timing here? Since you have to
> add the time for execution and bypassing it may get
> very tight. I think this kind of a hack should NEVER
> be taken for an bit width upward extensible core!!!
> Just my opinion though ;)

Please note that the execution units are pipelined.  There are registers
at the beginning, at the end and in the middle (for a 2-stage unit,
as shown).  Thus, execution and transport times do not add up.

-- 
 Michael "Tired" Riepe <Michael.Riepe@stud.uni-hannover.de>
 "All I wanna do is have a little fun before I die"
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