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Re: [f-cpu] Register Bank



hi !

Juergen Goeritz wrote:
> On Fri, 3 Aug 2001, Michael Riepe wrote:
> 
> > On Fri, Aug 03, 2001 at 09:29:06AM +0200, Juergen Goeritz wrote:
> > [...]
> > > Did you try to synthesize this yet?
> >
> > Are you kidding?  That's quick-and-dirty demo code, just enough to give
> > you people something to talk (and hopefully also think) about.
> 
> But just a small synthesize will give you an idea of the
> complexity in a real implementation. In VHDL it's small
> and easy but onchip it may be an awfull lot. I remember
> Armstrong saying something like "It's just a small step
> for me but a big one for mankind". Ok, a bit off-topic :-)

i am currently writing the register set part of QDCPOC2.
it doesn't look much like what was posted here, in C or VHDL.
i'll soon make an attempt to post a VHDL file.

basicly, the register set is split into 5 "banks" with individual
write enables. what is even more difficult is how to handle the
flags in parallel. The reason is that i have not practiced VHDL
for a long time :-/

you'll have to be patient, comprehensive, and hint me to the errors
or mistakes that i've made.

> JG
WHYGEE
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