Re: [f-cpu] Register Bank

[Yann Guidon <whygee@f-cpu.org>]

hi !

Kim Enkovaara wrote:
> 
> > wouldn't be sufficient anyway with its poor 96 MB of RAM).  When Nico
> > tried to synthesize the multiplier on his Suns, he also ran into memory
> > limitations (1 GB is not enough for such a big unit if one turns on some
> > optimization bells & whistles during the run).  So, if you can provide
> > access to a multi-gigabyte multi-gigahertz multi-CPU system and a set
> 
> If necessary I can sometimes run some test synthesis runs with DC if you
> can provide DC script file for the compilation. I have access to 4G and 8G
> Suns that have DC (and hopefully bigger ones in future :)).

i'm sure that nico will highly apreciate ! :-)))

> For FPGA implementation the multiplier can be a problem. Hand
> optimized version might not be optimal with FPGAs. For example Synplify
> does usually better results is the multiplication if it is just told with
> * operator. Synplify has excellent multiplier synthesis. It creates much
> faster multipliers than for exmaple Xiling core generator.

cool, but ...
 * what about non-FPGA targets ?
 * what about SIMD mutliplies ?
there are a lot of other (silly) questions but i'll let the "big guyz"
play with their toys alone :-) i am still struggling with QDCPOC2...

read you,

> Mr. Kim Enkovaara   | kim.enkovaara@iki.fi | Microelectronic Riemannian
WHYGEE
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