[f-cpu] register set BIST

[Yann Guidon <whygee@f-cpu.org>]

hi,

tonight i started designing the BIST for the register set.

coding in C is getting very frustrating and i would like to do some
more VHDL, if possible with a synthesiser behind... but i can't
have all that on my laptop :-)

back to the BIST : i do not test (yet) both write ports
(only one, maybe the second if we duplicate the BIST)
or the individual write enables. However, within a few thousand
of cycles, my method can check any fault that occurs in the
64*63=4032 bits of the bank.

I have started this design a few hours ago but i am confident
that, when run at reset, it will both test the bank and reset it.

However, i will need everyone's help to design the register bank.
its 5 write enables (per write port) makes it a delicate piece
of code, and we have to make the flag updates and other stuffs...

WHYGEE
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