[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
Re: [f-cpu] Scheduler
nicO wrote:
> I send you a scheme of a bypass net.
>
> The "Active" signal is the number of the active unit. On the same
> pipeline stage, there is only one active unit. For each active stage, i
> compare the address of the 2 write registers to the 2 registers in use
> by the instructions of the stage. I only drawn the system for one
> register (not the 3 read register) and only for one pipeline stage.
>
> I try to make a more clear one.
thanks,
but i do not understand everything.
giving signal types and names would be helpful, for example.
Is it a "simple bypass" or something more sophisticated ?
> nicO
WHYGEE
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
*************************************************************
To unsubscribe, send an e-mail to majordomo@seul.org with
unsubscribe f-cpu in the body. http://f-cpu.seul.org/