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Re: [f-cpu] Re: Floating-Point



Yann Guidon a écrit :
> 
> hi,
> 
> nicO wrote:
> > Yann Guidon a écrit :
> > > nicO wrote:
> > > > Yann Guidon a écrit :
> > > <>
> > > > > Currently i need hints about core generators for the register set.
> > > > > i don't know precisely how to handle the partial writes and the speed
> > > > > i can get.
> > > > Typically register bank could be seen as multiported SRAM memory. So
> > > > it's hard for me to understand why you need 5 flags to write back the
> > > > registers. When you write back a none SIMD 8 bit result does the 56
> > > > other bits remain unchange or are zeroed ?
> > >
> > > in our case, the 5 write masks are "write enable"s. so if the bit
> > > is not set, you don't update the register subfield. In fact, i think
> > > that the "lazy way" is a set of 5 banks of 63 registers, each with
> > > 2 common register write addresses but with 1 write enable bit per bank.
> > > Of course, semi-manual layout would help, but it would be too easy ...
> >
> > 5 banks ???
> > I beleive that conventionnal 8*8 bits (=64 bits) SRAM would be enought
> > (8 banks with 64 registers of 8 bits).
> > You need to decode the 5 lines to set the 8 enable line.
> 
> from the user point of view, there are 2 banks of 8 bit and 3 banks of 16 bits.
> at our level, it is not difficult to mimic a 16-bit bank with 2x8-bit banks.
> Now my problem is : how well does this synthesises ? how do you write this is VHDL ?
> Can we use a macro generator ?
> 

Take the description of the ff from Michael use a stdlogic_vector for
the signal. You just decode wich register are concerne before.

I think you should look to the code of the leon (see www.gaisler.com),
there are greate number of examples inside.

> > nicO
> > > > nicO
> > > WHYGEE
> WHYGEE
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