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Re: [f-cpu] the wrong way (or not?)



On Tue, 28 Aug 2001, Yann Guidon wrote:

> LEON serving as "service processor" for the F-CPU is
> cool but there must be a way to handle the bandwidth and
> clock speed difference : the F-CPU works with 256-bit wide
> cache lines and is clocked at least 2x faster (with the
> same silicon process, as a rough estimate). You'll have
> to put two or four LEONs in your desktop box to make a
> balanced system.

How do you know how well F-CPU will clock before the RTL code is done :)
Or has someone made already some rough estimations about the logic
deepness in each pipeline stage and estimations about the critical paths
inside pipeline. That could give some hints about the speed.

btw. for FPGA emulation there might be a need to do the ALU differently.
In FPGA architecture ALU must be designed around the 4-input LUT (many
architectures use 4 input). This limitation leads to a design where the
logical and aritcmetical ALUs are implemented separately etc. In this way
the logic deepness can be one logic level less (at least). But I'm not a
expert on this, there have been some discussions about this in
comp.arch.fpga or comp.lang.vhdl or verilog areas.

=============================================================================
Mr. Kim Enkovaara   | kim.enkovaara@iki.fi | Microelectronic Riemannian
Vasamatie 1 C 16    | IRC: embo            | curved-space fault in
02630 Espoo         |                      | write-only file system

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