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Re: [f-cpu] the wrong way (or not?)



On Tue, Aug 28, 2001 at 08:56:28AM +0300, Kim Enkovaara wrote:
[...]
> btw. for FPGA emulation there might be a need to do the ALU differently.
> In FPGA architecture ALU must be designed around the 4-input LUT (many
> architectures use 4 input). This limitation leads to a design where the
> logical and aritcmetical ALUs are implemented separately etc. In this way
> the logic deepness can be one logic level less (at least). But I'm not a
> expert on this, there have been some discussions about this in
> comp.arch.fpga or comp.lang.vhdl or verilog areas.

I wish you guys would at least read the F-CPU documentation and/or the
available source code before you waste my time.

- there is no single ALU
- logical operations are handled by the ROP2 execution unit
- add/subtract are done in the ASU EU
- the multiplier also is a separate unit
- the ROP2 is 1 stage "deep"
- the ASU needs 2 stages (for a full-width result)
- the IMU (integer multiply) currently has 6 stages

They're not optimized for FPGA use yet (which FPGA?  They differ so
much that you need to rewrite all your stuff when you move from one
vendor/family to another).

-- 
 Michael "Tired" Riepe <Michael.Riepe@stud.uni-hannover.de>
 "All I wanna do is have a little fun before I die"
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