Re: [f-cpu] New snapshot for EU_INC and EU_CMP

[Michael Riepe <michael@stud.uni-hannover.de>]

On Thu, Aug 01, 2002 at 03:36:26AM +0200, Yann Guidon wrote:
[...]
> > The instruction we need is `cmpl', aka `CoMPare Less' (A < B).
> > 
> > > I think that is more simple, and permit to win one or more level
> > > latency.
> > >
> > > But, my unit is not compliant to the manual. What must we correct :
> > > manual or code ?
> > 
> > Since the semantics of scan/lsb/msb seem to have changed behind my
> > back, we will have to discuss that here. CMP/MIN/MAX/SORT is wrong,
> > however.
> 
> LSB and MSB are needed in some cases but these algorithm do not
> justify an additional pipeline cycle on CMP. When POPC is implemented,
> it is "cheaper" to run the result from LSB into POPC.

MSBx is the *fastest* instruction the EU_CMP can compute. The second
stage (in my version) looks like this:

	- MSBx:
		a row of 32-input OR gates (d=3)

	- CMP:
		A row of AND2 gates, followed by a 64-input OR gate (d=4)

	- SORT:
		same as CMP, followed by a row of 2:1 MUXes (d=5)

Dropping or re-defining MSBx doesn't change the timing of the unit.

> Giving an "integer" number of 1 bits was just pure convenience,
> but the structure of the reduce-tree (and the tight pipeline)
> force us to use another simpler approach.

No they don't. We just won't be able to do it in 1 cycle.
NONE of the instructions.

> I even agree that some parts of the manual are science fiction.

Yep. Some are pretty real, though.

-- 
 Michael "Tired" Riepe <Michael.Riepe@stud.uni-hannover.de>
 "All I wanna do is have a little fun before I die"
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