Re: Rep:Re: [f-cpu] Manual 0.2.6

[cedric <cedric.bail@free.fr>]

Le Vendredi 2 Août 2002 15:15, Michael Riepe a écrit :
> On Fri, Aug 02, 2002 at 12:46:28PM +0000, Nicolas Boulay wrote:
> [...]
>
> > > >         cshiftl r3, r2, r1      // r1 = r2 << (64 * r3)
> > > >         cshiftr r3, r2, r1      // r1 = r2 >> (64 * r3)
> > > >
> > > > This can probably be integrated with the SHL execution unit.
> > >
> > > Why not using the SIMD flag ? And do :
> > >  r1 = r2 << ([8|16|32|64]*r3)
> >
> > Too complicated.
> >
> > >>> From hardware point of view ? You need in fact 4 shifters. I beleive
> > such shifter are smaller than a true 64 bits one.
> > Maybe the 16 bits version could be implemented (sizeof the loadcons).
>
> I don't want to make the control logic too complex. Therefore, the basic
> shift count (= chunk size) will have to be fixed. If it were variable,
> I also had to scale (that is, shift) the second operand in front of the
> control logic part.

I think you are right, because we have the mix/expand instruction. Currently 
we must do something like this for 8 bits :
	mixl.b r1, r2, r9
	mixl.b r3, r4, r10
	mixl.b r5, r6, r11
	mixl.b r7, r8, r12
	mixl.d r9, r10, r13
	mixl.d r11, r12, r14
	mixl.q r13, r14, r15

7 cycles for 8 chunks, that's quite good. So no need of a more complex 
instruction for small chunk and the cshift[l/r] will be enough (perhaps a 
immediate version will be usefull).

Cedric
	
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