[f-cpu] SR security

[cedric <cedric.bail@free.fr>]

Hi,

	Because on the F-CPU all the security depend on TLB and SR, we need to 
discuss about them. 
	About SR, I think that we have 2 differents class of SR, the one that can 
only be read and the other than can be read and write. The one that are 
readed can be readed by a lot of normal program, I mean that we will have 
some SR for the Floating Point (rouding flags, ...) for example. And you must 
have a quick access to them.
	For the others, they can be slow, because write on them can change the 
internal state of the CPU. Finally we must access to both of them with the 
immediate form of GET/PUT.

	Why not using the LSB to determine if the SR is read only or not ?

	In the manual, we currently have some specified SR : TLB_OFF, GET_CMB,
GET_VM (I think we have : FAMILY, STEPPING, MAX_SIZE, SIZE_0, SIZE_1, SIZE_2,
SIZE_3, MAX_CHUNK_SIZE, CYCLE, IRQ_BASE, IRQ_SIZE, TRAP_BASE, TRAP_SIZE,
SYSCALL_BASE, SYSCALL_SIZE, URL, URL_SIZE, TIME_SLICE, CMB_NEXT, CMB). In 
fact we must clarify them, TLB_OFF is really usefull. We didn't need  GET_CMB 
and GET_VM has defined into the manual. We currently have an other strange 
SR : TLBMISS_BASE (For me it's a trap). And I didn't understood the meaning of
PAGING and CONTROL.
	What I think we need to add :
		- READ_ONLY, that say if we must trap or not when we access 
to read only SR
		- WRITE_ONLY, idem but for read/write SR
		- ASI, the Identifier of the current task
		- IRQ_STACK_BASE and IRQ_STACK_SIZE, for being able to handle 
multiple IRQ at the same time
		- TRAP_STACK_BASE and TRAP_STACK_SIZE, in case of multiple TRAP
(I think it's not usefull, because the trap handler must do his job correctly)
		
	So it's a resume of what I read in the last snapshot from Whygee, in the 
manual and what we say on the mailing list. I hope I didn't forget or 
missunderstand something.

Cedric

PS: my objective it's to start adding a SR map for the next release of the 
manual so that thinking to port an OS like L4 can start.
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