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Re: [f-cpu] Too much option
On Thu, Aug 22, 2002 at 10:10:06PM +0200, Cedric BAIL wrote:
> Hi,
>
> I am currently working on a new release of the manual with the new color
> code for ISA and an OP_CODE map. I discover that we have 2048 possibles
> versions of the F-CPU, because we have a lot of optionals instructions.
> All the immediate form are optional, mix/expand/sdup are optional too. For me
> they must be include in all F-CPU compatible chip and we must reduce the number
> of possible version of F-CPU chip. I agree that LNS and FPU must be optional,
> but for increment based operation I think it's really too much usefull to be
> optional.
> What did you think about this problem ?
I guess mix/expand/sdup and the increment based ops can be made mandatory.
> I update shift instructions too and I discover that they have 2 unused bits.
> Why not using them to say :
> 00 => double shift right
> 01 => shift right
> 10 => shift left
> 11 => double shift left
>
> The problem will be with immediate, in that case we can use 2 operandes one for
> normal shift the other for dshift. (rot instructions have 2 unused bits too, so
> we can use them in the same way). It can save a lot of OP_CODE. (I quickly
> count them, and we have approximatively 100 different OP_CODE).
It may also work if their immediate counterparts use 6-bit constants
(instead of 8-bit ones).
> For the next release I want to insert widen instructions, but I read in a
> precedent mail that michael didn't like the way he describe it or something
> like that. Is it possible to have a little description on them ?
That's still undecided. It will probably become something like
widen[s].[bdq] r2, r1
with semantics equivalent to the C cast operations
r1 = (signed/unsigned char)r2 // 8 bit (.b)
r1 = (signed/unsigned short)r2 // 16 bit (.d)
r1 = (signed/unsigned int)r2 // 32 bit (.q)
where the destination size is always 64 bits.
--
Michael "Tired" Riepe <Michael.Riepe@stud.uni-hannover.de>
"All I wanna do is have a little fun before I die"
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