Re: [f-cpu] Conditionnal load and store, the return

["Christophe Avoinne" <christophe.avoinne@laposte.net>]

----- Original Message -----
From: "Cedric BAIL" <cedric.bail@free.fr>
To: <f-cpu@seul.org>
Sent: Saturday, August 24, 2002 4:49 PM
Subject: Re: [f-cpu] Conditionnal load and store, the return


> > > I have reread the discussion about conditionnal load and store, and I
> > > think that we forgot something : exception. In fact when we do a load
> > > or a store and check the condition only on write.
>
> > Spoken about the bit in a LSU0 entry telling us if we can write ? if it
> > is like a write-right token, setting it to 1 allows the first one to
reset
> > it and have right to write. If an exception occurs at this place, it
means
> > that there is no matching LSU0 entry (am I wrong ?), so there is no
right
> > to write and condition fails. Meanwhile, the exception is executed. At
> > exception exit, condition fails so we can reexecute the faulty
> > conditional store instruction.
>
> In fact we were speaking about a possible store[z/nz/m/l/nm/nl] and
> load[z/nz/m/l/nm/nl] instructions. And the problem was that currently the
> test is checked on wright, that mean you do first load the data and then
you
> verify if the test is ok.

load the data ? what data ? the conditional load only to need access to
memory if condition is true, so even an exception occurs, when reexecuting
the faulty instruction, all is okay. Same thing for the conditional store.
So i don't see any problem.

I maybe miss something.

 The problem is that if you access to a not valid

> But in fact we still have a problem with the conditional store/load with
> the LSU test in multi processor architecture.
>

Again, I don't see any problem.

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