Re: [f-cpu] Conditionnal load and store, the return

["Christophe Avoinne" <christophe.avoinne@laposte.net>]

----- Original Message -----
From: "Cedric BAIL" <cedric.bail@free.fr>
To: <f-cpu@seul.org>
Sent: Tuesday, August 27, 2002 3:03 AM
Subject: Re: [f-cpu] Conditionnal load and store, the return


> > load the data ? what data ? the conditional load only to need access
> > to memory if condition is true, so even an exception occurs, when
> > reexecuting the faulty instruction, all is okay. Same thing for the
> > conditional store.
> > So i don't see any problem.
>
> You will not reexecute it. I mean the conditionnal store on wich we
> discuss test if the condition register is zero or not, or if the lsb/msb
> if zero or not and if the test is true, the write is done. If you load
> a data conditionnaly, if the address isn't ok, and the test is false, no
> exeption must occur and it's where the problem is.
>

'load' : you mean you always load the value from memory and assign the value
to the data register only if test is succeeded ? well, if so, an exception
will occur before any test anyway. But you still must reexecute. Page fault
exception must point on the faulty instruction and must resume the faulty
instruction since we suppose we've just resolved the fault, so the program
can continue as if there was no fault. It is the behavior you will find on
all CPU for mmu management. Otherwise, you wouldn't be able to virtualize
memory.

But if you only access memory just after the test succeeds, an exception
will occur and still you need to rexecute the instruction.

So there is no problem for me because when resuming from a page fault
exception, you must reexecute the faulty instruction. It cannot be
otherwise.

'store' : you cannot store the value of a data register until the test
succeeds. So an exception only can happen after a succeeded test.

Anyway, if an exception occurs, all operation must abort, because it would
be resumed once exiting exception.

Because your instruction has no internal state. You cannot use partial
execution with exception. After an exception occurs, you cannot finish an
instruction by resuming partial execution : you need to reexecute the
instruction.

> > Again, I don't see any problem.
>
> Currently if you have this :
>
> [DATA]
>    |
> [CPU 1]---[CPU 2]
>
>
> When CPU2 do a conditional load/Store pair, it will not be abble to see
> if CPU 1 access to the data. The only reason why CPU 2 know that, is
because
> all memory access will always be send to CPU 2 by CPU 1... It can be a
> big overkill. I perhaps miss something but the problem exist.

Ok you are speaking about inter-cpu locking, not intra-cpu locking. Well of
course it is the most difficult problem to solve.

CPU1 and CPU2 can access directly to DATA, because they both have a
different LSU we are stuck.

In fact, the problem only occurs when you want a bi-processor or more, so I
think you an extra stuff to allow global locking of data between CPU.

I suppose you want several CPU able to access the same DATA directly :

CPU1------------------\
CPU2------------------+------DATA
CPU3------------------+
CPU4------------------/

You need a bridge to access DATA for all CPU. It cannot be possible for all
CPU to access DATA meanwhile.

Just an idea : beside the LSU for each CPU (internal LSU), we can have a
external LSU which only contains the locked entries :

if a CPU do normal load/store, just bypass external LSU : faster behavior.
if a CPU do lock load, set a new entry in external LSU.
if a CPU do lock store, check if entry is in external LSU.

This external LSU can be seen as a special memory.

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