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Re: [f-cpu] tlb last ! (secure bit, lib ring)




----- Original Message -----
From: "Michael Riepe" <michael@stud.uni-hannover.de>
To: <f-cpu@seul.org>
Sent: Thursday, August 29, 2002 2:25 PM
Subject: Re: [f-cpu] tlb last ! (secure bit, lib ring)


> > If I take the example of SH3, it has two TLBs, one for ICACHE, another
for
> > DCACHE. A valid entry in TLB associated with ICACHE has only X bit
> > (equivalent to R bit for data) because the instruction fetcher never
writes
> > data. A valid entry in TLB associated with DCACHE has R and W bits, but
not
> > X bit because the data fetcher never executes an instruction. So if you
> > intend to have a seperate TLB for ICACHE and DCACHE, it makes no sense
to
> > have a different bit for X and R IN THE TLB ENTRY.
> >
> > You want a general R,W,X with U/S pairing. Okay, but I still don't
> > understand because it is up to the software to handle them and not to
TLB.
>
> Access violations can (and will) be handled in software, but they can
> not be *detected* in software, unless you want to run an exception
> handler for *every* memory access.
>
> Note that the absence of a TLB entry means something different.
>
> And yes, we always want all three bits (rwx).
>

I know very well that. But you were talking if there is only one TLB which
can be used for code or data page. It hurts me for the reasons I gave above.
From the viewpoint of programmer we have those three bits, but from ITLB or
DTLB we dont need them all in the same TLB; r,w go in DTLB, and x goes in
ITLB. I just want for you to give a better detail of what kind of TLB fcpu
will use. Anyway, you always have your three bits but it is not really an
hardware issue (as I told bit x and bit r don't need to be in different
position since TLB entry are not the same in ITLB as in DTLB). I hope you
understand why now I insist on the fact we should be more clear about what
kind of TLB it must be and avoid some confusion about fixing three bits in
TLB entry, which is not very relevant to me. Quite now, I feel as if you
(people in general) have not an exact viewpoint of what TLB in FCPU should
be. Unless speaking of unified TLB for ICACHE and DCACHE - are you sure it
is a good thing ? most cpu avoid that - you really need to split your TLB
into ITLB and DTLB and have relevant description for each TLB : it is only
my concern. Be sure I'm not against all three bits.

Regards.



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