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Re: [f-cpu] ASIC vs FPGA vs Emulation vs simulation



On Wed, 27 Aug 2003, Yann Guidon wrote:

> 1) The VHDL is not compatible.  We had to completely rewrite ours.

Usually the best way is to write portable VHDL for the normal case. Then 
add additional views for the optimized versions and use for example 
configurations to select the correct views. The different views can be 
checked against eachother with formav equvalence tools for example. 

The simulation speed of the high level view is usually very good and the 
optimized versions can be very slow to simulate. Also all memory models 
should be inside wrappers to enable easy changes.

> 2) The libraries are different and not compatible.

One shouldn't try to write design as a netlist using one target library. 
That is not even wise with asics, because in new processes the libraries 
are quite moving target.

> 3) No matter what, you'll end up optimizing (size and/or speed) for the 
> FPGA.  Those optimizations will further hinder re-use.

That is the reason why in the initial versions you shouldn't optimize for 
FPGA. Just write good RTL code and let the synthezier do as good job as it 
can. And usually it is much better than exotic own versions of the blocks.

> 4) Emulated clock speed is more like 2 MHz (FPGAs are great for point 
> designs but not for emulation).

My experience is that you can get quite easily 1/4..1/8 of ASIC clock 
speed with FPGAs. And that applies if same generation of chips are 
compared.

>  - either we concentrate on "portable-only code" that is useful
> only for high-level simulation (everybody can use it but it's slow)
> and synthesis (almost nobody can use it),

Current synthesizers can do actually quite good results from portable 
code. It's no use writing your own adder when the synthesizer does very 
good job at selecting correct implementations for each FPGA architecture 
(correct carry chain structures etc.)

>  - or we decide to implement some code in FPGA, thus jeopardizing
> portability and dropping "Freedom" from the project names, just
> so early physical implementations can be used for hacking.

FPGA optimized code is usually not very good for ASIC implementation. So 
pure FPGA optimization can be quite bad road.

--Kim

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