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Re: [f-cpu] F-CPU architecture...



What I mean is the registers instead of being accessed by routes, all listen to the address bus and act when they are called. They particularly whatch for the link instruction. Then they store their temporary address. They can also track how many accesses have occured across the whole register set. 
link r1, r2, instr. The link instruction tells r2 to watch for accesses to r1.

The instr parameter then allows the register to perform a special instruction every so many accesses.

I admit maybe I just have a fascination with self modifying architectures.

 




 
----- Original Message -----
From: "Yann Guidon" <whygee@xxxxxxxxx>
To: f-cpu@xxxxxxxx
Subject: Re: [f-cpu] F-CPU architecture...
Date: Sat, 27 Aug 2005 17:25:51 +0200

> 
> hi,
> 
> Rares Marian wrote:
> 
> > Just a bizarre thought:
> > What if instead of moving data, the registers reassigned their 
> > own addresses so that data would appear to have moved?
> >
> >
> you mean : "register renaming" ?
> in FC0, this would almost kill the remaining performance ...
> This would add one or two stages at the beginning of the pipeline,
> thus doubling the penalty of a branch.
> So we'll have to include branch prediction etc....
> and i don't count other things like all the register renaming mechanisms
> which would consume even more silicon.
> Now, balance that with the performance gain
> which i estimate is near zero for FC0.
> 
> YG
> 
> 
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