[Author Prev][Author Next][Thread Prev][Thread Next][Author Index][Thread Index]
Re: CRC (was Re: [f-cpu] F-CPU architecture...)
Hi F-gang,
Yann Guidon wrote:
2) CRC is not considered as an instruction for F-CPU
(there are too many versions, so that would be very troublesome for no
almost benefit)
Well, there is a general formula. But that would require that the crc is
computed bitwise, which would take too long. It could handle at most two
or three bits per F-CPU pipeline stage - and we need to support at least
32 bits. A carefully designed software implementation may actually be
faster. Does anyone care enough to try it out?.
However, putting a CRC32 in the "DMA/blitter engine" would be way cool
(that would require a 32-bit field in the block descriptor with
additional flags
like "set/verify"; "irq on error", "valid/invalid CRC" etc.)
You mean, one could DMA some data to /dev/null and let the engine
calculate or verify the CRC? Then we don't need a CRC instruction. :-)
I/O bus transfers should always include a checksum for verification
anyway. But on the other hand, that need not be a programmable CRC,
which makes its implementation a lot easier.
--
Michael "Tired" Riepe <michael@xxxxxxxx>
X-Tired: Each morning I get up I die a little
*************************************************************
To unsubscribe, send an e-mail to majordomo@xxxxxxxx with
unsubscribe f-cpu in the body. http://f-cpu.seul.org/