[f-cpu] Understanding the FC0 pipeline

[Yann Guidon <whygee@f-cpu.org>]

hello,

I got a copy of the CDROM that is given with the book
"The Anatomy of a Microprocessor: A Systems Perspective"
by Shriver and Smith.
I am currently reading the pile of paper re-prints
including a lot of crucial and interesting stuff from the IEEE.

I'm currently reading a paper from James E. Smith,
written in 1985 while working for CDC on the CYBER 180/990.
It deals with precise exception in an out-of-order completion
pipelined machine and it will certainly be of greatest interest 
to nicolas because it also describes the scheduler which is
almost identical to this in FC0. However it was written
nearly 15 years before FC0 started and the principle is still
the same :-)

Note that some method diverge after a few pages, because we
deal with precise exceptions (principally page miss) in a different
way (split address computation and data fetch intructions).

But it's funny anyway to read a nearly FC0 description from
a CDC guy :-) They call "result shift register" what i call
"scheduler queue" (or something like that). The difference
is that FC0 has 2 result buses but the flags are the same :
(here i copy from the paper) 
  - "functional unit source" (it commands the MUX that selects
      which EU writes to the corresponding bus)
  - "Destination register" (it commands the register set's write
      address)
  - "valid bit" which says whether a "slot" is free or not.
It even adds a new data which points to a sophisticated
reordering table for renaming, but it's only at the end of the paper.

I love reading those old papers : even though i tend to
reinvent the wheel, at least it recomforts me in seeing that
i was not obviously wrong :-)

I am experiencing troubles uploading the PDF
on the seul.org server at http://f-cpu.seul.org/new.
This paper will also be on the CCC F-CPU CDROM.

WHYGEE
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