Re: [f-cpu] FC0's RTL scheduler

[Michael Riepe <michael@stud.uni-hannover.de>]

On Wed, Dec 19, 2001 at 03:56:06AM +0100, Yann Guidon wrote:
[...]
> maybe we can "cheat" with the scheduler : swap the register number,
> instead of the data, and validate one or another ? it can save one cycle
> at the "cost" of missing some issue opportunities but they can be recovered
> with a careful coding uideline. what do you think ?

Not sufficient. E.g. for a 16-bit operation, the result chunks come out
like this:

	high part:	33221100
	low  part:	33221100

For `macl.16' the low part *should* be "11110000" ("33332222" for
`mach.16'), according to the manual. That's one of the reasons why I
never liked the original definition of the mac instruction.

> And can you explain a bit how the output ports work ?
> how many do you need ? And what about the normal operations ?

You need one or two of them for each operation. The low part is used for
both `mul' and `mulh', the high part for `mulh' only (and for `macl/`mach'
you'll have to take both and mix them -- or I'll have to add more ports).

Results always arrive on their corresponding ports, that is, 32-bit
results will be available at the 32-bit outputs after 5 cycles. Due to
the `forked' pipeline and the different latencies, multiple results
may appear at the same time, e.g. at t=0 you may get a 64-bit
result (instruction issued at t=-6), a 32-bit result (started at
t=-5), and upper or lower parts of 16-bit and 8-bit computations.
Of course the scheduler can avoid that if the Xbar is unable to handle
the traffic.

I guess I'll have to delay the 8- and 16-bit low parts by 1 cycle (to
make high and low parts arrive at the same time). Otherwise, scheduling
becomes a nightmare.

-- 
 Michael "Tired" Riepe <Michael.Riepe@stud.uni-hannover.de>
 "All I wanna do is have a little fun before I die"
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