[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

[f-cpu] 3r2w -> 2r1w



We have soon speak about that. I beleive that Whygee was ok about it.
But a recent post seems to say the opposite.

So i propose to change all reference in the manual concerning register
access as rn and rn+1 by rn with n even and rn+1. So why ? 

Because it became possible to have only 3 port to access the register
bank instead of 5. Most of 3r2w instructions only need an access to a
Rn+1 register, this add 2 complete new access port to the memory and a
incrementer unit.

If we align access, we can manage 128 bits data path. so in fact, each
register are packed by 2. So all instruction which need more than a
register will use the close one. If we want access to a single register
we simply use a muxes.

There is 2 main point to use less access port : -the speed of the
regiter bank and -the avability of such memory.

The more port you put on a memory, slower it run, that's physical.
Usualy silicon foundry give memory generator for dual ported memory and
nothing else (it the same for FPGA). So (as for leon), we could use 2
area of such memory to produice the 3 needed port for the memory (so we
duplicat data). In fact, asking the foundry to give specific item cost a
lot of money, so at least for the Fc0, i should consider that fact.

I jnmy compagny they will use leon. And will never have money to ask to
have multiported memory (don't even think of using array of flipflop if
you want speed !!).

So each EU could receive 2 128 bits data and write ONE 128 data. Write
enable could be used to minimise power consumption when only one byte is
written.

Comments ?

nicO
*************************************************************
To unsubscribe, send an e-mail to majordomo@seul.org with
unsubscribe f-cpu       in the body. http://f-cpu.seul.org/