Re: Re: [f-cpu] GCC 3.1 for F-CPU port

[devik <devik@cdi.cz>]

> >> at least, using these numbers is not ambiguous at all.
> >
> >Probably because .8 is valid ONLY if SR_SIZE_0 == 1 ...
>
> and what ?

ehm .. if you use .8 => SIZE_BITS(00) and run with SR_SIZE_0=16 ....
it will do something unexpected (unless assembler emit that it
expects SR_SIZE_0 is 8) :)

> There is also a little convention : SR_SIZE_3 contains
> the largest size. This way, algorithms that need the largest
> size (for maximal performance) do not need to fiddle with
> SRs. But this can be changed or enhanced.

Let me speculate a bit. You want forward compatible CPU. So
if one compiles program for 64 bit FC0 he assumes SR_SIZE_3=64
(or 4 or 8 - I'm not sure with semantics).
If you now have 128bit FC0 (will it be still FC0?) then you
could still run that program - OS loader will load SR_SIZE
map from ELF PHDR and apply it for given task. But here
SR_SIZE_3=64 not 128 so that the convention doesn't hold.

> > I should not rely on bits 8 and higher, these can have
> > any value, correct ?
>
> now, the mask clears the MSB so you can rely on this to be zero.

Hmm .. but then the code will not be compatible with CPUs
which don't implement the masking.
Will it be mandatory on all F-CPUs to clear it ?

devik

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