[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

Re: [f-cpu] Zen and the art of F-CPU assembler coding



On Tue, Dec 10, 2002 at 12:13:16PM +0100, devik wrote:

> One more idea/question, the ROP2 3->4 decoder is placed in
> xbar stage. If `n -> 2**n' decoders would take too many time,
> at least immediate form (which is the most used one for bit flag
> manipulation) can be done by moving decoders (or pipelinable part
> of them) to xbar stage too.

Don't worry, there is enough room. There will also be enough room to
move the 3->4 decoder out of the Xbar into the ROP2 where it belongs.
A 6->64 decoder is approximately three gates deep, and none of them is
an XOR - that is less than 1/2 pipeline stage.

> Or do you know any important usage of non-immediate form
> with significant savings from shift+and/or method ?

I guess it's rarely needed, but I think we should provide it anyway.
All immediate binary operations have non-immediate counterparts,
and if it helps us save a register (for the mask) when registers
are short, its presence is already justified.

It will also be helpful in instruction emulators. Just in case someone
wants to execute his old x86/68k/PPC/SPARC binaries on the F-CPU :)

-- 
 Michael "Tired" Riepe <Michael.Riepe@stud.uni-hannover.de>
 "All I wanna do is have a little fun before I die"
*************************************************************
To unsubscribe, send an e-mail to majordomo@seul.org with
unsubscribe f-cpu       in the body. http://f-cpu.seul.org/