Re: [f-cpu] Relative branch

[whygee@club-internet.fr]

hi !

>Date: Wed, 11 Dec 2002 11:29:38 +0100 (CET)
>De: devik <devik@cdi.cz>
>A: <f-cpu@seul.org>
>Sujet: [f-cpu] Relative branch
>
>Just short idea, I was found that in compiled
>code for fcpu is missing shorter/faster jump.

well, it's not exactly "missing", it must be made
by a sequence of instructions...

>Why dont we have jump which instead of registers
>to use as return address save and target adres
>have instead 12bit immediate which would REPLACE
>lower 8 bits (for example) of IP.

huh ... because in FC0, the IP is "virtual".
there is no such register implemented in HW.
Instead, the IP is "generated" by the instruction
fetch buffer from several fields in the cache line.

>There is no problem with TLB because smallest page
>is 4k (12bits) so that we could jump only in the same
>page. It also meand no adder is needed.

yup but jumping across pages are not possible.
And that behaviour would change depending on the page size
(well, i try to forecast this case).

>Compiler would emit appropriate .align for the code.
>This would help small conditional branches, save
>code size and register usage ...

but what about speed ?

the goal is to spread the jump code, because it
is simply impossible to jump in a single cycle.

Imagine that you have a cjump instruction with a new
address' LSB, you have to
 - fetch the address (several cycles)
 - check the condition in parallel
 - decode the new instruction
 etc.
At least, the "split branch", even if it takes several
instructions, hides some of the pipeline bubble's size.
And this is easily "factored" because in loops or other
codes, you can fetch once and jump to that position
from several places.

But yes, the intent was not to fit directly with GCC.
but it's not too complex and not too slow. The rest is
"SW issues"... :-P

>devik
YG

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