Rep:Re: Rep:Re: Rep:Re: [f-cpu] signed cmpl

["Nicolas Boulay" <nicolas.boulay@ifrance.com>]

-----Message d'origine-----
De: devik <devik@cdi.cz>
A: <f-cpu@seul.org>
Date: 20/12/02
Objet: Re: Rep:Re: Rep:Re: [f-cpu] signed cmpl

> > So that 202 insns ARE in 6bit range but these was constants 1 and -1
> > often (addi) - I didn't implemented INC/DEC yet. There was 82 of
such.
> > As conclusion from 275 immediates 120 (202-82) can be coded into
> > 6 bits.
>
> And from that, how much can't use the actual 8 bits version (because 2
> flag bitsdisappear ?)

I'm afraid I have not understood your question. Are you asking for insn
whose need more than 8 bits ?

>>>Nop.
Now it exist an instruction format using 8 bits immediats by stolen 2
bits in the flag field of the instruction word. I don't like it because
it stole those 2 bits, so not every reg-reg->reg instructions could use
8 bits immediat. 6 bits will do it. So what is the number of
instructions using immediat between -32 and 32 and that can't use the 8
bits immediat version of each instruction because it miss those 2 flag
bits.

devik

*************************************************************
To unsubscribe, send an e-mail to majordomo@seul.org with
unsubscribe f-cpu       in the body. http://f-cpu.seul.org/
_____________________________________________________________________
Envie de discuter en "live" avec vos amis ? Télécharger MSN Messenger
http://www.ifrance.com/_reloc/m la 1ère messagerie instantanée de France

_____________________________________________________________________
GRAND JEU SMS : Pour gagner un NOKIA 7650, envoyez le mot IF au 61321
(prix d'un SMS + 0.35 euro). Un SMS vous dira si vous avez gagné.
Règlement : http://www.ifrance.com/_reloc/sign.sms


*************************************************************
To unsubscribe, send an e-mail to majordomo@seul.org with
unsubscribe f-cpu       in the body. http://f-cpu.seul.org/