[Author Prev][Author Next][Thread Prev][Thread Next][Author Index][Thread Index]

Re: [f-cpu] dynamic code reuse



To answer your question it will be very hard to add to gcc.
One need to decide that "this" is block of code which will
probably produce repetable result ....

On Mon, 8 Dec 2003, Nicolas Boulay wrote:

> Imagine the instruction :
>
> WATCH R1,R2,R3, [PC + #imm] W1, W2
>
> R1,R2,R3, W1,W2 are register #imm is an immediat
>
> Those instruction act as :
>
> if (def cache{R1,R2,R3,PC})
> {
>  	fetch (PC + #imm)
> 	(W1,W2) = cache{R1,R2,R3,PC}
> }
> else
> {       fetch (PC+1)
> 	cache(R1,R2,R3,PC) = (W1,W2)@[PC + #imm] <- the result of registre W1,W2
>                                                       are cached at this point
> }
>
> It explicitly keep a result in a specific cache.
>
> nicO
>
> Le Lundi 8 Décembre 2003 18:25, devik a écrit :
> > You should post short example. I don't understand your idea yet.
> >
> > On Mon, 8 Dec 2003, Nicolas Boulay wrote:
> > > Le Dimanche 7 Décembre 2003 16:36, Michael Riepe a écrit :
> > > > On Sun, Dec 07, 2003 at 04:19:58PM +0000, Nicolas Boulay wrote:
> > > > > There is a branch of studies concerning the reuse of soon calculated
> > > > > value in code.
> > > > >
> > > > > http://citeseer.nj.nec.com/sodani97dynamic.html
> > > > >
> > > > > The idea from the paper is that there is always some result in the
> > > > > code that have been soon calculated. The idea is to reuse the result
> > > > > instead of recalulate it. Increase speed could reach 20%.
> > > > >
> > > > > This gave me an idea but with software support.
> > > > >
> > > > > This is a kind of jump instruction. The jump take some register and
> > > > > one adresse. If the content of the r register + the PC match a
> > > > > internal specific cache the result of 2w register is set and the jump
> > > > > occur.
> > > >
> > > > Sounds a lot like `speculative execution' to me.
> > > > Disclaimer: I didn't read the paper yet.
> > >
> > > nop this is a specultative reuse of a previous calculated result.
> > >
> > > > > To fill the cache, some thing "watch" the result calculated  where
> > > > > the instruction is supposed to jump. In case of interrupt, this is
> > > > > lost to avoid confusion and to stay stateless.
> > > > >
> > > > > This instruction needed to be handle carrefully by the compiler. So
> > > > > what's up in the area ?
> > > >
> > > > Rien, I suppose.
> > >
> > > Devik ? what's your opinion about this feature to implemented in the
> > > compiler ?
> > >
> > > nicO
> > >
>
> *************************************************************
> To unsubscribe, send an e-mail to majordomo@seul.org with
> unsubscribe f-cpu       in the body. http://f-cpu.seul.org/
>
>

*************************************************************
To unsubscribe, send an e-mail to majordomo@seul.org with
unsubscribe f-cpu       in the body. http://f-cpu.seul.org/