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[f-cpu] register set



hello,

the register set is almost finished. I still have to make
an exhaustive testbench and add the zero detector.
I have based the design on transparent latches,
they ensure that the cells are not too large and slow.
It's almost completely asynchronous : reading is just
combinational (the address is driven by the fetcher's
output register) while writing is driven by the scheduler
queue's output. the write command of each cell is given
by the address decoder ANDed with the write mask,
so writing is allowed when the mask is enabled and the
data remain when the mask goes low. There are certainly
some setup&hold conditions to ensure but it looks interesting.

Now i'm seeking real implementations and VHDL "wrappers"
of such a bank. I have looked a bit at the latest LEON sources
but they look too messy for me...

WHYGEE
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
PS: yes, i know, some people will shout at me because
i don't use fully synchronous logic, but the register set would
otherwise be larger and consume more power ... and i'm not
afraid of semi-custom optimisations ;-P </troll deflektor>
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