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Re: [f-cpu] vhdl2c 0.1



On Mon, Feb 11, 2002 at 06:26:10AM +0100, Yann Guidon wrote:
[...]
> Back to the original reason of my post : Cedric claims that he can do
> full-system simulations in his school, given the hundreds of 1GHz Athlon on
> a 100mbps network. I however claim that
>  - the network is the bottleneck
>  - VHDL simulations are not easily parallelisable.

It may be possible to parallelize simulation of large, modular
circuits. The trick might be to use separate global and local state,
and multiple event queues. But that's a special solution that can't be
generalized. And we would have to write our own cluster-enabled simulator.

> A globaly adressable, distributed memory multiprocessor might give better
> results thanks to faster synchronisation, better internal bandwidth and
> smaller OS overhead.

Yep.

> But franckly, if we do our job correctly, we wouln't even need that ...
> a good management of the events can half the simulator's activity
> (and even the power consumption due to the decrease of activity).
> A good example is the multiplier : the input data latch should memorise
> operands only when a multiply operation is wanted. This prevents the
> whole multiply pipeline to oscillate with the Xbar's value. This thus
> avoids the simulator's event queue to fill uselessly.

Already implemented (except the input register). The pipeline registers
will not switch unless they have to (that is, unless there is valid data
in that particular stage).

-- 
 Michael "Tired" Riepe <Michael.Riepe@stud.uni-hannover.de>
 "All I wanna do is have a little fun before I die"
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