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Re: [f-cpu] register set



hello,

Kim Enkovaara wrote:
> > I have based the design on transparent latches,
> > they ensure that the cells are not too large and slow.
> > It's almost completely asynchronous : reading is just
> > combinational (the address is driven by the fetcher's
> 
> Have you tought about test structures for ASIC manufacturing? Latches are
> never fun thing to test. D-flipflops are so much easier to test with
> normal scan paths.

concerning the R7 testing, i have an algorithm in mind that does not
use scanpaths. It is implemented inside the BIST unit but before
i go into details, it is :
 - faster
 - better
 - full speed (will catch HF-related faults like unwanted Xtalk or capacitance)
 - not dependent on an external scan controller

On the production line, the BIST will detect a lot of faults but
after bonding/packaging, some special software will have to run
anyway, to catch faults that can't be detected otherwise, for
specific control signals for example... But yes, i design with
100% testability in mind. We even learn the basics at the university,
but what BIST will implement is derived from my work at a previous
position...

> --Kim

then, Ben Franchuk wrote:
> Kim Enkovaara wrote:
<snip>
> How ever Latches are 1/2 the size of flip-flops.
certainly but ...

the size of a "memory cell" (a set of 4 transistors)
is small compared to the rest of the control logic
that will read from 2 signals and select where to write
(3 tristate buffers). One latch is almost the size
of one tristate buffer so the important difference
is in latching latency and "timing" (the sequence
of signal levels).
first, compared to a D flip-flop, a latch
requires less transitions of the control signal.
This is "good" for the operating frequency and
the power consumption.
Sencond, the written data is ready sooner than for
a D flip-flop (the latch is transparent).
So for me it doesn't look "evil".

One of my worries is the design of a single cell.
while i can layout a single latch, a 3R2W cell is
a bit more complex...

By the way, if people are "eager" to have a D-ff,
i could probably reuse the dual-edge flip-flop idea
and adapt it a bit...

> I like latches as data
> flows through them but flip-flops stop the data flow until a good bit
> after the clock. Regardless scan paths are hard to test and design as
> your scan logic messes up your data logic.

The BIST unit is designed for this task. It seems that a
scanpath is only needed for those bits that are out of the
classical datapath, such as protection and configuration bits,
cache and memory control...

> Ben Franchuk - Dawn * 12/24 bit cpu *
 * and still running *
WHYGEE
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