Re: [f-cpu] No latches, please !

[Yann Guidon <whygee@f-cpu.org>]

after your "no outlook", the "no latches" outcry :-)

nicolas.boulay@ifrance.com wrote:
> I have miss that : please NO LATCH in our design !!!!

hey, these are only electrons flowing in computers...
no death, no harm, no anger... :-)

> It's almost useless compare to classique flip-flop.
as i explained in another message
the size argument is not a problem because a 4-T cell
is not orders of magnitude smaller than a FF.
Most of the size is taken by the wires (5 in each direction,
2 for the write ports and 3 for the read ports).

however the problem comes from the timing...

> I have said nothing for the register set because of the speed.
i don't get this. Can you explain ?

> But latch are generaly a very very bad idea.
really ?

> It's almost impossible to test correctly and a lot of
> tools have problem with them (static timing analysis,
> compiler ...).
"if the tools are broken, it ain't the design" ;-P

btw, i care for the 100% testing, if you were still not reassured
by previous messages.

> -----Message d'origine-----
> De: Yann Guidon <whygee@f-cpu.org>
> A: f-cpu@seul.org
> Date: 11/02/02
> Objet: Re: [f-cpu] vhdl2c 0.1
> A good example is the multiplier : the input data
> latch should memorise

oooops !

now i get it : it's only an abuse of langage here.
i was just speaking about timing issues...
please forgive me !

clock gating or write enables will do fine here,
but now that you speak about it... why use clock gating
when latches are smaller and do the same ? :-P


ok i stop here, it becomes difficult to differenciate
between humor and trolling.

However, if someone can write a portable "multiport ram block"
that can be reused in F-CPU (and maybe even for other things
than registers), everybody will be happy !

WHYGEE
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