Rep:Re: [f-cpu] non standard cell

[<nicolas.boulay@ifrance.com>]

-----Message d'origine-----
De: "Marco Al" <marco@simplex.nl>
A: <f-cpu@seul.org>
Date: 13/02/02
Objet: Re: [f-cpu] non standard cell

From: <nicolas.boulay@ifrance.com>

>>>>> Only one compagny could create a new cells for
their technology, the one who maid it. If an other
compagny, want to create such new things it will pay
... a lot ! (because ST, IBM, UMC, TEMIC,... should
relance a complete series of teste before you could
used it !)

What do you call cell's? A quick google search turned
up that UMC provides

>>>> I said "cells" for what is often called gate but
it's more generic(and, nand gate, muxes, complete
adder, 2-bits adder, flipflop,... ). A gate level
design (produice by synthetiser) is the connection
between a collection of such cells.
nicO

something they call Pcell's for instance
(http://www.cadence.com/datasheets/umc_foundry_proces
s_design_kits.html).

>>>>That's the tools to create new cells.

Of course there's plenty of other tools out there
which let you do custom
cell design, are you saying physical simulation using
transistor level
process characterization has become so poor you have
no hope of getting
custom designs right in one go anymore?

Marco

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